Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die

ABSTRACT

A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

CLAIM TO DOMESTIC PRIORITY

The present application is a continuation of U.S. patent applicationSer. No. 12/714,190, filed Feb. 26, 2010, which is acontinuation-in-part of U.S. patent application Ser. No. 12/565,380,filed Sep. 23, 2009, now U.S. Pat. No. 8,143,097, which application isincorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and,more particularly, to a semiconductor device and method of forming aninterposer with an open cavity to contain a semiconductor die in a waferlevel chip scale package.

BACKGROUND OF THE INVENTION

Semiconductor devices are commonly found in modern electronic products.Semiconductor devices vary in the number and density of electricalcomponents. Discrete semiconductor devices generally contain one type ofelectrical component, e.g., light emitting diode (LED), small signaltransistor, resistor, capacitor, inductor, and power metal oxidesemiconductor field effect transistor (MOSFET). Integrated semiconductordevices typically contain hundreds to millions of electrical components.Examples of integrated semiconductor devices include microcontrollers,microprocessors, charged-coupled devices (CCDs), solar cells, anddigital micro-mirror devices (DMDs).

Semiconductor devices perform a wide range of functions such ashigh-speed calculations, transmitting and receiving electromagneticsignals, controlling electronic devices, transforming sunlight toelectricity, and creating visual projections for television displays.Semiconductor devices are found in the fields of entertainment,communications, power conversion, networks, computers, and consumerproducts. Semiconductor devices are also found in military applications,aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices exploit the electrical properties of semiconductormaterials. The atomic structure of semiconductor material allows itselectrical conductivity to be manipulated by the application of anelectric field or base current or through the process of doping. Dopingintroduces impurities into the semiconductor material to manipulate andcontrol the conductivity of the semiconductor device.

A semiconductor device contains active and passive electricalstructures. Active structures, including bipolar and field effecttransistors, control the flow of electrical current. By varying levelsof doping and application of an electric field or base current, thetransistor either promotes or restricts the flow of electrical current.Passive structures, including resistors, capacitors, and inductors,create a relationship between voltage and current necessary to perform avariety of electrical functions. The passive and active structures areelectrically connected to form circuits, which enable the semiconductordevice to perform high-speed calculations and other useful functions.

Semiconductor devices are generally manufactured using two complexmanufacturing processes, i.e., front-end manufacturing, and back-endmanufacturing, each involving potentially hundreds of steps. Front-endmanufacturing involves the formation of a plurality of die on thesurface of a semiconductor wafer. Each die is typically identical andcontains circuits formed by electrically connecting active and passivecomponents. Back-end manufacturing involves singulating individual diefrom the finished wafer and packaging the die to provide structuralsupport and environmental isolation.

One goal of semiconductor manufacturing is to produce smallersemiconductor devices. Smaller devices typically consume less power,have higher performance, and can be produced more efficiently. Inaddition, smaller semiconductor devices have a smaller footprint, whichis desirable for smaller end products. A smaller die size may beachieved by improvements in the front-end process resulting in die withsmaller, higher density active and passive components. Back-endprocesses may result in semiconductor device packages with a smallerfootprint by improvements in electrical interconnection and packagingmaterials.

Wafer level chip scale module packages (WLCSMP) and fan-out wafer levelchip scale packages (FO-WLCSP) typically contain stacked semiconductordie over and between an organic substrate or interposer for higherdevice integration. Examples of the WLCSMPs with upper and lower stackedsemiconductor die can be found in U.S. Pat. Nos. 6,921,968, 5,977,640,and 6,906,415. The lower semiconductor die is thinner than the organicsubstrate and thus contained within the encapsulant. Accordingly, it isdifficult to properly dissipate heat from the lower semiconductor. Thefixed organic substrate requires care when handling to avoid damage tothe thin semiconductor die. In addition, warpage is a recurring issuedue to mismatches in the coefficient of thermal expansion (CTE) betweenthe upper and lower semiconductor die and organic substrate.

In FO-WLCSP, the bumps on the upper semiconductor die are typicallylarge in diameter with a corresponding high pitch. The large pitch ofupper die bumps limits the ability to mount a fine-pitch die with highinput/output (I/O) count. In addition, the bump collapse for large ballsis difficult to control, particularly when mounted on adhesive tape orcarrier. The bump collapse increases chances of electrical shorting toadjacent conductive structures during reflow. The lower semiconductordie is prone to shifting during encapsulation due to inadequate adhesionbetween die and carrier.

SUMMARY OF THE INVENTION

A need exists for a thinner WLCSP to accommodate a fine-pitch die withhigh I/O count. Accordingly, in one embodiment, the present invention isa method of making a semiconductor device comprising the steps ofproviding a carrier, forming an interface layer over the carrier,disposing a first substrate over the carrier, disposing a secondsubstrate over the carrier, disposing a first semiconductor die over thefirst and second substrates electrically connected to the first andsecond substrates, depositing an encapsulant over the firstsemiconductor die and over the first and second substrates, and removingthe carrier and interface layer.

In another embodiment, the present invention is a method of making asemiconductor device comprising the steps of providing a firstsubstrate, disposing a second substrate adjacent to the first substrate,disposing a first semiconductor die over the first substrateelectrically connected to the first substrate, and depositing anencapsulant over the first semiconductor die and over the first andsecond substrates.

In another embodiment, the present invention is a semiconductor devicecomprising a first substrate and a second substrate. A firstsemiconductor die is disposed over the first and second substrates. Anencapsulant is deposited over the first semiconductor die and over thefirst and second substrates.

In another embodiment, the present invention is a semiconductor devicecomprising a first substrate and a second substrate. A firstsemiconductor die is disposed over the first and second substrates andelectrically connected to the first and second substrates.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a PCB with different types of packages mounted to itssurface;

FIGS. 2 a-2 c illustrate further detail of the representativesemiconductor packages mounted to the PCB;

FIGS. 3 a-3 i illustrate a process of forming a WLCSMP having an opencavity for containing a semiconductor die and interconnected through aTSV interposer;

FIG. 4 illustrates the WLCSMP with an open cavity containing thesemiconductor die and interconnected through the TSV interposer;

FIG. 5 illustrates the TSV interposer with a polymer insulating layer;

FIG. 6 illustrates the WLCSMP with a heat spreader and TIM layer formedover the upper semiconductor die;

FIG. 7 illustrates the WLCSMP with an EMI and RFI shielding layer formedover the upper semiconductor die;

FIG. 8 illustrates the WLCSMP with conductive pillars formed through theencapsulant;

FIG. 9 illustrates the WLCSMP with conductive pillars formed through theencapsulant and conductive layer formed over the encapsulant;

FIG. 10 illustrates the WLCSMP with conductive pillars formed throughthe encapsulant and interconnect structure formed over the uppersemiconductor die;

FIG. 11 illustrates the WLCSMP with TSV formed through the uppersemiconductor die and interconnect structure formed over the uppersemiconductor die;

FIG. 12 illustrates the WLCSMP with TSV formed through the lowersemiconductor die and interconnect structure formed over the lowersemiconductor die;

FIGS. 13 a-13 g illustrate a process of forming an interposer with anopening for containing a semiconductor die;

FIG. 14 illustrates the FO-WLCSP with interposer having an opening forcontaining the semiconductor die;

FIG. 15 illustrates conductive TSV formed in the lower semiconductordie;

FIG. 16 illustrates conductive pillars formed in the encapsulant aroundthe upper semiconductor die;

FIG. 17 illustrates the WLCSMP with an EMI and RFI shielding layerformed over the upper semiconductor die;

FIG. 18 illustrates a truncated interposer with encapsulant formed onthe sides of the FO-WLCSP;

FIG. 19 illustrates discrete semiconductor components formed over theinterposer;

FIG. 20 illustrates two-level stepped interposer with openings forcontaining two semiconductor die;

FIG. 21 illustrates an upper interposer stacked over a lower interposerwith openings for containing two semiconductor die; and

FIG. 22 illustrates two-level stepped interposer with openings forstacking three semiconductor die.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in thefollowing description with reference to the figures, in which likenumerals represent the same or similar elements. While the invention isdescribed in terms of the best mode for achieving the invention'sobjectives, it will be appreciated by those skilled in the art that itis intended to cover alternatives, modifications, and equivalents as maybe included within the spirit and scope of the invention as defined bythe appended claims and their equivalents as supported by the followingdisclosure and drawings.

Semiconductor devices are generally manufactured using two complexmanufacturing processes: front-end manufacturing and back-endmanufacturing. Front-end manufacturing involves the formation of aplurality of die on the surface of a semiconductor wafer. Each die onthe wafer contains active and passive electrical components, which areelectrically connected to form functional electrical circuits. Activeelectrical components, such as transistors and diodes, have the abilityto control the flow of electrical current. Passive electricalcomponents, such as capacitors, inductors, resistors, and transformers,create a relationship between voltage and current necessary to performelectrical circuit functions.

Passive and active components are formed over the surface of thesemiconductor wafer by a series of process steps including doping,deposition, photolithography, etching, and planarization. Dopingintroduces impurities into the semiconductor material by techniques suchas ion implantation or thermal diffusion. The doping process modifiesthe electrical conductivity of semiconductor material in active devices,transforming the semiconductor material into an insulator, conductor, ordynamically changing the semiconductor material conductivity in responseto an electric field or base current. Transistors contain regions ofvarying types and degrees of doping arranged as necessary to enable thetransistor to promote or restrict the flow of electrical current uponthe application of the electric field or base current.

Active and passive components are formed by layers of materials withdifferent electrical properties. The layers can be formed by a varietyof deposition techniques determined in part by the type of materialbeing deposited. For example, thin film deposition may involve chemicalvapor deposition (CVD), physical vapor deposition (PVD), electrolyticplating, and electroless plating processes. Each layer is generallypatterned to form portions of active components, passive components, orelectrical connections between components.

The layers can be patterned using photolithography, which involves thedeposition of light sensitive material, e.g., photoresist, over thelayer to be patterned. A pattern is transferred from a photomask to thephotoresist using light. The portion of the photoresist patternsubjected to light is removed using a solvent, exposing portions of theunderlying layer to be patterned. The remainder of the photoresist isremoved, leaving behind a patterned layer. Alternatively, some types ofmaterials are patterned by directly depositing the material into theareas or voids formed by a previous deposition/etch process usingtechniques such as electroless and electrolytic plating.

Depositing a thin film of material over an existing pattern canexaggerate the underlying pattern and create a non-uniformly flatsurface. A uniformly flat surface is required to produce smaller andmore densely packed active and passive components. Planarization can beused to remove material from the surface of the wafer and produce auniformly flat surface. Planarization involves polishing the surface ofthe wafer with a polishing pad. An abrasive material and corrosivechemical are added to the surface of the wafer during polishing. Thecombined mechanical action of the abrasive and corrosive action of thechemical removes any irregular topography, resulting in a uniformly flatsurface.

Back-end manufacturing refers to cutting or singulating the finishedwafer into the individual die and then packaging the die for structuralsupport and environmental isolation. To singulate the die, the wafer isscored and broken along non-functional regions of the wafer called sawstreets or scribes. The wafer is singulated using a laser cutting toolor saw blade. After singulation, the individual die are mounted to apackage substrate that includes pins or contact pads for interconnectionwith other system components. Contact pads formed over the semiconductordie are then connected to contact pads within the package. Theelectrical connections can be made with solder bumps, stud bumps,conductive paste, or wirebonds. An encapsulant or other molding materialis deposited over the package to provide physical support and electricalisolation. The finished package is then inserted into an electricalsystem and the functionality of the semiconductor device is madeavailable to the other system components.

FIG. 1 illustrates electronic device 50 having a chip carrier substrateor printed circuit board (PCB) 52 with a plurality of semiconductorpackages mounted on its surface. Electronic device 50 may have one typeof semiconductor package, or multiple types of semiconductor packages,depending on the application. The different types of semiconductorpackages are shown in FIG. 1 for purposes of illustration.

Electronic device 50 may be a stand-alone system that uses thesemiconductor packages to perform one or more electrical functions.Alternatively, electronic device 50 may be a subcomponent of a largersystem. For example, electronic device 50 may be a graphics card,network interface card, or other signal processing card that can beinserted into a computer. The semiconductor package can includemicroprocessors, memories, application specific integrated circuits(ASIC), logic circuits, analog circuits, RF circuits, discrete devices,or other semiconductor die or electrical components.

In FIG. 1, PCB 52 provides a general substrate for structural supportand electrical interconnect of the semiconductor packages mounted on thePCB. Conductive signal traces 54 are formed over a surface or withinlayers of PCB 52 using evaporation, electrolytic plating, electrolessplating, screen printing, or other suitable metal deposition process.Signal traces 54 provide for electrical communication between each ofthe semiconductor packages, mounted components, and other externalsystem components. Traces 54 also provide power and ground connectionsto each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels.First level packaging is a technique for mechanically and electricallyattaching the semiconductor die to an intermediate carrier. Second levelpackaging involves mechanically and electrically attaching theintermediate carrier to the PCB. In other embodiments, a semiconductordevice may only have the first level packaging where the die ismechanically and electrically mounted directly to the PCB.

For the purpose of illustration, several types of first level packaging,including wire bond package 56 and flip chip 58, are shown on PCB 52.Additionally, several types of second level packaging, including ballgrid array (BGA) 60, bump chip carrier (BCC) 62, dual in-line package(DIP) 64, land grid array (LGA) 66, multi-chip module (MCM) 68, quadflat non-leaded package (QFN) 70, and quad flat package 72, are shownmounted on PCB 52. Depending upon the system requirements, anycombination of semiconductor packages, configured with any combinationof first and second level packaging styles, as well as other electroniccomponents, can be connected to PCB 52. In some embodiments, electronicdevice 50 includes a single attached semiconductor package, while otherembodiments call for multiple interconnected packages. By combining oneor more semiconductor packages over a single substrate, manufacturerscan incorporate pre-made components into electronic devices and systems.Because the semiconductor packages include sophisticated functionality,electronic devices can be manufactured using cheaper components and astreamlined manufacturing process. The resulting devices are less likelyto fail and less expensive to manufacture resulting in a lower cost forconsumers.

FIGS. 2 a-2 c show exemplary semiconductor packages. FIG. 2 aillustrates further detail of DIP 64 mounted on PCB 52. Semiconductordie 74 includes an active region containing analog or digital circuitsimplemented as active devices, passive devices, conductive layers, anddielectric layers formed within the die and are electricallyinterconnected according to the electrical design of the die. Forexample, the circuit may include one or more transistors, diodes,inductors, capacitors, resistors, and other circuit elements formedwithin the active region of semiconductor die 74. Contact pads 76 areone or more layers of conductive material, such as aluminum (Al), copper(Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and areelectrically connected to the circuit elements formed withinsemiconductor die 74. During assembly of DIP 64, semiconductor die 74 ismounted to an intermediate carrier 78 using a gold-silicon eutecticlayer or adhesive material such as thermal epoxy or epoxy resin. Thepackage body includes an insulative packaging material such as polymeror ceramic. Conductor leads 80 and wire bonds 82 provide electricalinterconnect between semiconductor die 74 and PCB 52. Encapsulant 84 isdeposited over the package for environmental protection by preventingmoisture and particles from entering the package and contaminating die74 or wire bonds 82.

FIG. 2 b illustrates further detail of BCC 62 mounted on PCB 52.Semiconductor die 88 is mounted over carrier 90 using an underfill orepoxy-resin adhesive material 92. Wire bonds 94 provide first levelpackaging interconnect between contact pads 96 and 98. Molding compoundor encapsulant 100 is deposited over semiconductor die 88 and wire bonds94 to provide physical support and electrical isolation for the device.Contact pads 102 are formed over a surface of PCB 52 using a suitablemetal deposition process such as electrolytic plating or electrolessplating to prevent oxidation. Contact pads 102 are electricallyconnected to one or more conductive signal traces 54 in PCB 52. Bumps104 are formed between contact pads 98 of BCC 62 and contact pads 102 ofPCB 52.

In FIG. 2 c, semiconductor die 58 is mounted face down to intermediatecarrier 106 with a flip chip style first level packaging. Active region108 of semiconductor die 58 contains analog or digital circuitsimplemented as active devices, passive devices, conductive layers, anddielectric layers formed according to the electrical design of the die.For example, the circuit may include one or more transistors, diodes,inductors, capacitors, resistors, and other circuit elements withinactive region 108. Semiconductor die 58 is electrically and mechanicallyconnected to carrier 106 through bumps 110.

BGA 60 is electrically and mechanically connected to PCB 52 with a BGAstyle second level packaging using bumps 112. Semiconductor die 58 iselectrically connected to conductive signal traces 54 in PCB 52 throughbumps 110, signal lines 114, and bumps 112. A molding compound orencapsulant 116 is deposited over semiconductor die 58 and carrier 106to provide physical support and electrical isolation for the device. Theflip chip semiconductor device provides a short electrical conductionpath from the active devices on semiconductor die 58 to conductiontracks on PCB 52 in order to reduce signal propagation distance, lowercapacitance, and improve overall circuit performance. In anotherembodiment, the semiconductor die 58 can be mechanically andelectrically connected directly to PCB 52 using flip chip style firstlevel packaging without intermediate carrier 106.

FIGS. 3 a-3 i illustrate, in relation to FIGS. 1 and 2 a-2 c, a processof forming a WLCSMP having an open cavity for containing a semiconductordie and interconnected through TSV interposer. FIG. 3 a shows asemiconductor wafer 118 containing a base substrate material, such assilicon, germanium, gallium arsenide, indium phosphide, or siliconcarbide, for structural support. A plurality of vias is formed fromsurface 123 partially through semiconductor wafer 118 using laserdrilling, mechanical drilling, or etching process, such as deep reactiveion etching (DRIE) or potassium hydroxide (KOH) etch. An optionalinsulating layer can be formed around the vias as a liner. Afterdepositing the insulation layer inside the vias, the vias are filledwith Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), W, poly-silicon, or othersuitable electrically conductive material using PVD, CVD, electrolyticplating, electroless plating, or other suitable metal deposition processto form conductive through silicon vias (TSV) 122.

A circuit layer 124 is formed over surface 123 of semiconductor wafer118. Circuit layer 124 contains an electrically conductive layer 125separated by insulating layer 126. The insulating layer 126 can be oneor more layers of silicon dioxide (SiO2), silicon nitride (Si3N4),silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide(Al2O3), photoresist, or other material having similar insulating andstructural properties. The insulating layer 126 is formed using PVD,CVD, printing, spin coating, spray coating, sintering or thermaloxidation. A portion of insulating layer 126 is removed by an etchingprocess. Conductive layer 125 is formed in the removed portions ofinsulating layer 126 using patterning with PVD, CVD, sputtering,electrolytic plating, electroless plating, or other suitable metaldeposition process. Conductive layer 125 can be one or more layers ofAl, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductivematerial. One portion of conductive layer 125 is electrically connectedto TSV 122. Other portions of conductive layer 125 can be electricallycommon or electrically isolated depending on the design and function ofthe semiconductor device. One or more integrated passive devices (IPD),such as inductors, capacitors, and resistors, can be formed in circuitlayer 124 for RF signal processing.

A trench or cavity 128 is formed from surface 123 partially throughsemiconductor wafer 118 with sufficient width and depth to contain asemiconductor die. Trench 128 can be formed with saw blade, laserdrilling, mechanical drilling, DRIE, or KOH etch. In one embodiment,trench 128 has a width greater than an x/y axis length of thesemiconductor die and depth greater than a thickness of thesemiconductor die. An optional trench 130 is formed from surface 123partially through semiconductor wafer 118 for dicing saw space. Trench130 allows the sides of semiconductor wafer 118 (later referred to asTSV interposer) to be covered by encapsulant after singulation.

A substrate or carrier 120 contains temporary or sacrificial basematerial such as silicon, polymer, polymer composite, metal, ceramic,glass, glass epoxy, beryllium oxide, or other suitable low-cost, rigidmaterial for structural support. An interface layer or tape 121 isapplied over carrier 120 as a temporary adhesive bonding film oretch-stop layer.

FIG. 3 b shows semiconductor wafer 118 mounted to carrier tape 121 withsurface 123 oriented away from the tape. In another embodiment, TSV 122can be formed in semiconductor wafer 118 after to mounting the wafer tocarrier 120.

FIG. 3 c shows a semiconductor die or component 132 having an activesurface 133 containing analog or digital circuits implemented as activedevices, passive devices, conductive layers, and dielectric layersformed within the die and electrically interconnected according to theelectrical design and function of the die. For example, the circuit mayinclude one or more transistors, diodes, and other circuit elementsformed within active surface 133 to implement analog circuits or digitalcircuits, such as digital signal processor (DSP), ASIC, memory, or othersignal processing circuit. Semiconductor die 132 may also contain IPD,such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive bump material is deposited over activesurface 133 using an evaporation, electrolytic plating, electrolessplating, ball drop, or screen printing process. The bump material can beAl, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, withan optional flux solution. For example, the bump material can beeutectic Sn/Pb, high-lead solder, or lead-free solder. The bump materialis reflowed by heating the material above its melting point to formspherical balls or bumps 136. Bumps 136 represent one type ofinterconnect structure that can be formed over active surface 133. Theinterconnect structure can also use stud bumps, micro bumps, conductivepillars, conductive paste, or other electrical interconnect.

A semiconductor die or component 134 is mounted and electricallyconnected to semiconductor die 132 using bumps 136. Semiconductor die134 has an active surface 135 containing analog or digital circuitsimplemented as active devices, passive devices, conductive layers, anddielectric layers formed within the die and electrically interconnectedaccording to the electrical design and function of the die. For example,the circuit may include one or more transistors, diodes, and othercircuit elements formed within active surface 135 to implement analogcircuits or digital circuits, such as DSP, ASIC, memory, or other signalprocessing circuit. Semiconductor die 134 may also contain IPD, such asinductors, capacitors, and resistors, for RF signal processing.

The combined semiconductor die 132-134 are positioned over semiconductorwafer 118 and aligned to place semiconductor die 134 over trench 128.The combined semiconductor die 132-134 are then mounted to semiconductorwafer 118 by reflowing bumps 136 to metallurgically and electricallyconnect active surface 133 to conductive layer 125, as shown in FIG. 3d. Semiconductor die 134 is contained within trench 128 to reduce thepackage height.

In FIG. 3 e, an encapsulant or molding compound 140 is deposited oversemiconductor wafer 118 and around semiconductor die 132 and 134 using apaste printing, compressive molding, transfer molding, liquidencapsulant molding, vacuum lamination, spin coating, or other suitableapplicator. Encapsulant 140 can be polymer composite material, such asepoxy resin with filler, epoxy acrylate with filler, or polymer withproper filler. Encapsulant 140 is non-conductive and environmentallyprotects the semiconductor device from external elements andcontaminants.

In FIG. 3 f, a portion of encapsulant 140 is removed by grinding wheel142 to expose a back surface 143 of semiconductor die 132 and reduce theheight of the package. In another embodiment, such as described in FIG.9, grinding wheel 142 can leave a portion of encapsulant 140 coveringsurface 143 of semiconductor die 132.

In FIG. 3 g, an optional substrate or carrier 144 contains temporary orsacrificial base material such as silicon, polymer, polymer composite,metal, ceramic, glass, glass epoxy, beryllium oxide, or other suitablelow-cost, rigid material or bulk semiconductor material for structuralsupport. An interface layer or tape 146 is applied over carrier 144 as atemporary adhesive bonding film or etch-stop layer. The assemblydescribed in FIGS. 3 a-3 f is inverted and mounted to carrier tape 146.The carrier 120 and tape 121 are removed by chemical etching, mechanicalpeel-off, CMP, mechanical grinding, thermal bake, laser scanning, or wetstripping.

In FIG. 3 h, a portion of surface 147 of semiconductor wafer 118,opposite surface 123, is removed by grinding wheel 142 to expose TSV 122and back surface 148 of semiconductor die 134 and reduce the height ofthe package. The remaining portion of semiconductor wafer 118constitutes interposer 149 having TSV 122 for electrical interconnect.

In FIG. 3 i, an interconnect structure 150 is formed over surface 151 ofinterposer 149. The interconnect structure 150 includes an insulating orpassivation layer 152 formed over surface 151 as using PVD, CVD,printing, spin coating, spray coating, sintering or thermal oxidation.The insulating layer 152 can be one or more layers of SiO2, Si3N4, SiON,Ta2O5, Al2O3, or other material having similar insulating and structuralproperties. A portion of insulating layer 152 is removed by an etchingprocess to expose TSV 122.

An electrically conductive layer 154 is formed over TSV 122 and theremoved portion of insulating layer 152 using a patterning anddeposition process such as PVD, CVD, sputtering, electrolytic plating,and electroless plating. Conductive layer 154 can be one or more layersof Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductivematerial. An optional under bump metallization (UBM) layer can be formedover conductive layer 154. One portion of conductive layer 154 iselectrically connected to TSV 122 and circuit layer 124. Other portionsof conductive layer 154 can be electrically common or electricallyisolated depending on the design and function of the semiconductordevice.

An electrically conductive bump material is deposited over build-upinterconnect structure 150 and electrically connected to conductivelayer 154 using an evaporation, electrolytic plating, electrolessplating, ball drop, or screen printing process. The bump material can beAl, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, withan optional flux solution. For example, the bump material can beeutectic Sn/Pb, high-lead solder, or lead-free solder. The bump materialis bonded to conductive layer 154 using a suitable attachment or bondingprocess. In one embodiment, the bump material is reflowed by heating thematerial above its melting point to form spherical balls or bumps 156.In some applications, bumps 156 are reflowed a second time to improveelectrical contact to conductive layer 154. The bumps can also becompression bonded to conductive layer 154. Bumps 156 represent one typeof interconnect structure that can be formed over conductive layer 154.The interconnect structure can also use stud bumps, micro bumps,conductive pillars, conductive paste, or other electrical interconnect.

The carrier 144 and tape 146 are removed by chemical etching, mechanicalpeel-off, CMP, mechanical grinding, thermal bake, laser scanning, or wetstripping. Semiconductor die 132 and 134 are singulated with saw bladeor laser cutting device 160 into individual WLCSMP. FIG. 4 shows WLCSMP162 after singulation. Discrete semiconductor components 164, such asresistor, capacitor, inductor, or active component, are mounted tointerposer 149. Semiconductor die 134 is electrically connected tosemiconductor die 132 through bumps 136. Semiconductor die 132 iselectrically connected through circuit layer 124 and interposer 149containing TSV 122 to interconnect structure 150. The WLCSMP 162 has anopen cavity for containing semiconductor die 134 to reduce the height ofthe package. The grinding process also reduces the height of WLCSMP 162.In one embodiment, the sides of interposer 149 are covered byencapsulant 140 due to the extra dicing space provided by trench 130.Alternatively, without trench 130, the sides of interposer 149 can beexposed. The exposed surface 143 of semiconductor die 132 and exposedsurface 148 of semiconductor die 134 provide for good heat dissipation.The similar base material of semiconductor die 132 and 134 andinterposer 149, e.g., silicon, provides thermal stress relief and makesWLCSMP 162 robust against any mismatch in CTE between the components ofthe package. Accordingly, WLCSMP 162 has reduced occurrence of warpage.

In a variation of the above process, after FIG. 3 h, an interconnectstructure 170 is formed over surface 151 of interposer 149, as shown inFIG. 5. The interconnect structure 170 includes a polymer insulatinglayer 172 formed over surface 151 using spin coating, film lamination,molding, or other suitable deposition process. Polymer insulating layer172 can be one or more layers of polyimide, benzocyclobutene (BCB),polybenzoxazoles (PBO), or other material having similar insulating andstructural properties. A portion of polymer insulating layer 172 isremoved by an etching process to expose TSV 122.

An electrically conductive layer 174 is formed over TSV 122 and theremoved portion of polymer insulating layer 172 using a patterning anddeposition process such as PVD, CVD, sputtering, electrolytic plating,and electroless plating. Conductive layer 174 can be one or more layersof Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductivematerial. One portion of conductive layer 174 is electrically connectedto TSV 122 and circuit layer 124. Other portions of conductive layer 174can be electrically common or electrically isolated depending on thedesign and function of the semiconductor device.

An electrically conductive bump material is deposited over build-upinterconnect structure 170 and electrically connected to conductivelayer 174 using an evaporation, electrolytic plating, electrolessplating, ball drop, or screen printing process. The bump material can beAl, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, withan optional flux solution. For example, the bump material can beeutectic Sn/Pb, high-lead solder, or lead-free solder. The bump materialis bonded to conductive layer 174 using a suitable attachment or bondingprocess. In one embodiment, the bump material is reflowed by heating thematerial above its melting point to form spherical balls or bumps 176.In some applications, bumps 176 are reflowed a second time to improveelectrical contact to conductive layer 174. The bumps can also becompression bonded to conductive layer 174. Bumps 176 represent one typeof interconnect structure that can be formed over conductive layer 174.The interconnect structure can also use stud bumps, micro bumps,conductive pillars, conductive paste, or other electrical interconnect.

FIG. 6 shows WLCSMP 178 including the features described in FIGS. 3 a-3i and 4 and metal plate 180 mounted to surface 143 of semiconductor die132 and encapsulant 140 with thermally conductive adhesive. Metal plate180 can also be formed by electroless or electroplating process. Metalplate 180 operates as a heat spreader to dissipate thermal energy fromWLCSMP 178. Metal plate 180 can be Al, Cu, or another material with highthermal conductivity. An optional die attach adhesive or thermalinterface layer (TIM) 182 secures metal plate 180 to semiconductor die132 and encapsulant 140. Metal plate 180 increases the rigidity ofWLCSMP 178.

FIG. 7 shows WLCSMP 190 including the features described in FIGS. 3 a-3i and 4 and metal plate 192 mounted to surface 143 of semiconductor die132 and encapsulant 140 with an adhesive. Metal plate 192 can also beformed by electroless or electroplating process. Metal plate 192operates as an electromagnetic interference (EMI) or radio frequencyinterference (RFI) shielding layer. Metal plate 192 can be Cu, Al,ferrite or carbonyl iron, stainless steel, nickel silver, low-carbonsteel, silicon-iron steel, foil, epoxy, conductive resin, and othermetals and composites capable of blocking or absorbing EMI, RFI, andother inter-device interference. The shielding layer can also be anon-metal material such as carbon-black or aluminum flake to reduce theeffects of EMI and RFI. Metal plate 192 is grounded through conductivepillars or studs 194, circuit layer 124, TSV 122 in interposer 149, andinterconnect structure 150. Conductive pillars 194 can be Au studs, orCu pillars, or solder. Metal plate 192 also operates as a heat spreaderto dissipate thermal energy from WLCSMP 190.

FIG. 8 shows WLCSMP 196 including the features described in FIGS. 3 a-3i and 4 and conductive pillars or studs 198 formed in encapsulant 140.Conductive pillars 198 can be formed by laser drilling, mechanicaldrilling, or DRIE vias in encapsulant 140 and filling the vias withconductive material, such as Cu, Au, or solder. Conductive pillars 198provide additional interconnect capability for stacking semiconductorpackages.

FIG. 9 shows WLCSMP 200 including the features described in FIGS. 3 a-3i and 4, with the exception that the grinding operation described inFIG. 3 f leaves encapsulant 140 covering surface 143 of semiconductordie 132. Conductive pillars or studs 202 can be formed by laserdrilling, mechanical drilling, or DRIE vias in encapsulant 140 andfilling the vias with conductive material, such as Cu, Au, or solder.Conductive layer 204 is formed in encapsulant 140. Conductive pillars202 and conductive layer 204 provide additional interconnect capabilityfor fan-in stacking semiconductor packages.

FIG. 10 shows WLCSMP 210 including the features described in FIGS. 3 a-3i and 4. In addition, conductive pillars or studs 212 can be formed bylaser drilling, mechanical drilling, or DRIE vias in encapsulant 140 andfilling the vias with conductive material, such as Cu, Au, or solder. Aninterconnect structure 214 is formed over surface 143 of semiconductordie 132 and encapsulant 140. The interconnect structure 214 includes aninsulating or passivation layer 216 formed using PVD, CVD, printing,spin coating, spray coating, sintering or thermal oxidation. Theinsulating layer 216 can be one or more layers of SiO2, Si3N4, SiON,Ta2O5, Al2O3, or other material having similar insulating and structuralproperties. An electrically conductive layer 218 is formed in insulatinglayer 216 using a patterning and deposition process such as PVD, CVD,sputtering, electrolytic plating, and electroless plating. Conductivelayer 218 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or othersuitable electrically conductive material. One portion of conductivelayer 218 is electrically connected to conductive pillars 212. Otherportions of conductive layer 218 can be electrically common orelectrically isolated depending on the design and function of thesemiconductor device. Conductive pillars 212 and interconnect structure214 provide additional interconnect capability for fan-in stackingsemiconductor packages.

FIG. 11 shows WLCSMP 220 including the features described in FIGS. 3 a-3i and 4. In addition, conductive pillars 222 can be formed by laserdrilling, mechanical drilling, or DRIE vias in semiconductor die 132 andfilling the vias with conductive material, such as Cu or Au. Aninterconnect structure 224 is formed over surface 143 of semiconductordie 132. The interconnect structure 224 includes an insulating orpassivation layer 226 formed using PVD, CVD, printing, spin coating,spray coating, sintering or thermal oxidation. The insulating layer 226can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or othermaterial having similar insulating and structural properties. A portionof insulating layer 226 is removed by an etching process. Anelectrically conductive layer 228 is formed in the removed portion ofinsulating layer 226 using a patterning and deposition process such asPVD, CVD, sputtering, electrolytic plating, and electroless plating.Conductive layer 228 can be one or more layers of Al, Cu, Sn, Ni, Au,Ag, or other suitable electrically conductive material. Conductivepillars 222 and conductive layer 226 provide additional interconnectcapability for stacking semiconductor packages.

FIG. 12 shows WLCSMP 230 including the features described in FIGS. 3 a-3i and 4. In addition, conductive pillars 232 can be formed by laserdrilling, mechanical drilling, or DRIE vias in semiconductor die 134 andfilling the vias with conductive material, such as Cu or Au. Theinterconnect structure 150 is extended over surface 148 of semiconductordie 134. Conductive pillars 232 and interconnect structure 150 oversurface 158 of semiconductor die 134 provide additional interconnectcapability for stacking semiconductor packages.

FIGS. 13 a-13 g illustrate, in relation to FIGS. 1 and 2 a-2 c, aprocess of forming an interposer with an opening for containing asemiconductor die. In FIG. 13 a, a wafer-form substrate or carrier 240contains temporary or sacrificial base material such as silicon,polymer, polymer composite, metal, ceramic, glass, glass epoxy,beryllium oxide, or other suitable low-cost, rigid material forstructural support. An interface layer or tape 242 is applied overcarrier 240 as a temporary double-sided adhesive bonding film oretch-stop layer.

In FIG. 13 b, a die-form laminate interposer 244 is mounted to interfacelayer 242 over carrier 240. The interposer 244 includes one or moreinsulating layers 246 and one or more conductive layers 248. Conductivelayer 248 provides a vertical conduction path through interposer 244.The openings 250 have sufficient width and depth to contain asemiconductor die.

FIG. 13 c shows a semiconductor die or component 252 having an activesurface 254 containing analog or digital circuits implemented as activedevices, passive devices, conductive layers, and dielectric layersformed within the die and electrically interconnected according to theelectrical design and function of the die. For example, the circuit mayinclude one or more transistors, diodes, and other circuit elementsformed within active surface 254 to implement analog circuits or digitalcircuits, such as DSP, ASIC, memory, or other signal processing circuit.Semiconductor die 252 may also contain IPD, such as inductors,capacitors, and resistors, for RF signal processing. Bumps 256 areformed on contact pads 258 which are electrically connected to thecircuits within active surface 254 of semiconductor die 252,

A semiconductor die or component 260 has an active surface 262containing analog or digital circuits implemented as active devices,passive devices, conductive layers, and dielectric layers formed withinthe die and electrically interconnected according to the electricaldesign and function of the die. For example, the circuit may include oneor more transistors, diodes, and other circuit elements formed withinactive surface 262 to implement analog circuits or digital circuits,such as DSP, ASIC, memory, or other signal processing circuit.Semiconductor die 260 may also contain IPD, such as inductors,capacitors, and resistors, for RF signal processing. Contact pads 264are electrically connected to the circuits on active surface 262 ofsemiconductor die 260.

Semiconductor die 260 is mounted to semiconductor die 252 with dieattach adhesive 268. The combined semiconductor die 252 and 260 arepositioned over interposer 244 and aligned to place semiconductor die260 over opening 250 with contact pads 264 oriented toward carrier 240.The combined semiconductor die 252 and 260 are then mounted tointerposer 244 by reflowing, thermal-compress bonding, or mechanicalplugging of bumps 256 to metallurgically and electrically connectcontact pads 258 to conductive layer 248, as shown in FIG. 13 d.Semiconductor die 260 is contained within opening 250 to reduce thepackage height.

In another embodiment, semiconductor die 260 is first mounted in opening250. Semiconductor die 252 is then mounted to semiconductor die 260 andinterposer 244 with die attach adhesive 268 and bumps 256.

In FIG. 13 e, an encapsulant or molding compound 270 is deposited overinterposer 244 and around semiconductor die 252 and 260 using a pasteprinting, compressive molding, transfer molding, liquid encapsulantmolding, vacuum lamination, spin coating, or other suitable applicator.Encapsulant 270 can be polymer composite material, such as epoxy resinwith filler, epoxy acrylate with filler, or polymer with proper filler.Encapsulant 270 is non-conductive and environmentally protects thesemiconductor device from external elements and contaminants.

In FIG. 13 f, carrier 240 and interface layer 242 are removed bychemical etching, mechanical peel-off, CMP, mechanical grinding, thermalbake, laser scanning, or wet stripping. A build-up interconnectstructure 274 is formed over semiconductor die 260 and interposer 244.The build-up interconnect structure 274 includes an insulating orpassivation layer 276 formed by PVD, CVD, printing, spin coating, spraycoating, or thermal oxidation. The insulating layer 276 can be one ormore layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polymer dielectric, orother material having similar insulating and structural properties. Anelectrically conductive layer 278 is formed using patterning and PVD,CVD, electrolytic plating, electroless plating process, or othersuitable metal deposition process. Conductive layer 278 can be one ormore layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electricallyconductive material. Conductive layer 278 is electrically connected toconductive layer 248 of interposer 244 and contact pads 264 ofsemiconductor die 260. Conductive layer 278 operates, in part, as aredistribution layer (RDL) to extend the electrical connectivity ofinterposer 244.

An electrically conductive bump material is deposited over build-upinterconnect structure 274 and electrically connected to conductivelayer 278 using an evaporation, electrolytic plating, electrolessplating, ball drop, or screen printing process. The bump material can beAl, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, withan optional flux solution. For example, the bump material can beeutectic Sn/Pb, high-lead solder, or lead-free solder. The bump materialis bonded to conductive layer 278 using a suitable attachment or bondingprocess. In one embodiment, the bump material is reflowed by heating thematerial above its melting point to form spherical balls or bumps 280.In some applications, bumps 280 are reflowed a second time to improveelectrical contact to conductive layer 278. The bumps can also becompression bonded to conductive layer 278. Bumps 280 represent one typeof interconnect structure that can be formed over conductive layer 278.The interconnect structure can also use stud bumps, micro bumps,conductive pillars, conductive paste, or other electrical interconnect.

Semiconductor die 252 and 260 are singulated with saw blade or lasercutting device 281 into individual FO-WLCSP 282. FIG. 14 shows FO-WLCSP282 after singulation. Semiconductor die 252 is electrically connectedto semiconductor die 260 through bumps 256, interposer 244, andconductive layer 278 of build-up interconnect structure 274. FO-WLCSP282 has interposer 244 with an open cavity for containing semiconductordie 260 to reduce the height of the package. Bumps 256 are relativelysmall, compared to bumps 280, which provides finer pitch and higher I/Ocount for semiconductor die 252. The smaller bumps 256 also improvescontrol of bump collapse and reduces electrical shorting to adjacentconductive structures. The interposer 244 reduces the encapsulant flowpressure toward semiconductor die 260 to reduce die shifting duringencapsulation.

FIG. 15 shows FO-WLCSP 290 similar to the features described in FIGS. 13a-13 g and 14 with conductive TSV 292 formed through semiconductor die260. A plurality of vias is formed through semiconductor die 260 overcontact pads 264 using laser drilling, mechanical drilling, or DRIE. Thevias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, orother suitable electrically conductive material using electrolyticplating, electroless plating process, or other suitable metal depositionprocess to form conductive TSVs 292 for vertical interconnectivity.Bumps 294 are formed between TSVs 292 and contact pads 258 to provideelectrical connection between semiconductor die 252 and semiconductordie 260.

FIG. 16 shows FO-WLCSP 296 similar to the features described in FIGS. 13a-13 g and 14 with conductive through mold vias (TMV) 298 formed throughencapsulant 270. A plurality of vias is formed through encapsulant 270over conductive layer 248 using laser drilling, mechanical drilling, orDRIE. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W,poly-silicon, or other suitable electrically conductive material usingelectrolytic plating, electroless plating process, or other suitablemetal deposition process to form conductive TMVs 298 for verticalinterconnectivity. TMVs 298 are electrically connected to conductivelayer 248 of interposer 244. In another embodiment, conductive pillars,stacked bumps, or studs are formed in encapsulant 270.

FIG. 17 shows FO-WLCSP 300 similar to the features described in FIGS. 13a-13 g and 14 with conductive TSV 302 formed through semiconductor die252. A plurality of vias is formed through semiconductor die 252 overcontact pads 258 using laser drilling, mechanical drilling, or DRIE. Thevias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, orother suitable electrically conductive material using electrolyticplating, electroless plating process, or other suitable metal depositionprocess to form conductive TSVs 302 for vertical interconnectivity.

A thermal interface material (TIM) 304 is applied over a back surface ofsemiconductor die 252, opposite active surface 254. A heat sink 306 ismounted over TIM 304 and the back surface of semiconductor die 252. Heatsink 306 can be Al, Cu, or another material with high thermalconductivity to provide heat dissipation for semiconductor die 252. TIM304 can be aluminum oxide, zinc oxide, boron nitride, or pulverizedsilver. TIM 304 aids in the distribution and dissipation of heatgenerated by semiconductor die 252 and 260.

FIG. 18 shows FO-WLCSP 308 similar to the features described in FIGS. 13a-13 g and 14 with interposer 244 truncated or singulated to removeopposing end portions of the interposer. An encapsulant or moldingcompound 309 is deposited over interposer 244 and around semiconductordie 252 and 260 using a paste printing, compressive molding, transfermolding, liquid encapsulant molding, vacuum lamination, spin coating, orother suitable applicator. Encapsulant 309 can be polymer compositematerial, such as epoxy resin with filler, epoxy acrylate with filler,or polymer with proper filler. Encapsulant 309 is non-conductive andenvironmentally protects the semiconductor device from external elementsand contaminants. Encapsulant 309 covers the sides of FO-WLCSP 308 foradditional protection.

FIG. 19 shows FO-WLCSP 310 similar to the features described in FIGS. 13a-13 g and 14 without semiconductor die 252. Discrete semiconductorcomponents 312 are mounted and electrically connected to conductivelayer 248 of interposer 244. Discrete semiconductor components 312 canbe active devices, such as transistors and diodes, or passive devices,such as capacitors, resistors, and inductors. The interposer 244prevents shifting of discrete semiconductor components 312 duringencapsulation.

An encapsulant or molding compound 311 is deposited over interposer 244and around semiconductor die 260 and discrete semiconductor component312 using a paste printing, compressive molding, transfer molding,liquid encapsulant molding, vacuum lamination, spin coating, or othersuitable applicator. Encapsulant 311 can be polymer composite material,such as epoxy resin with filler, epoxy acrylate with filler, or polymerwith proper filler. Encapsulant 311 is non-conductive andenvironmentally protects the semiconductor device from external elementsand contaminants.

FIG. 20 shows FO-WLCSP 314 similar to the features described in FIGS. 13a-13 g and 14 with two-level stepped interposer 316 having one or moreconductive layers 318 and one or more conductive layers 320 and one ormore insulating layers 322. Conductive layers 318 and 320 provide avertical conduction path through interposer 316. Conductive layer 318 iselectrically connected to conductive layer 278 of build-up interconnectstructure 274. Conductive layer 320 is electrically connected betweenbumps 256 and conductive layer 278.

An electrically conductive layer 324 is formed over interposer 316 andencapsulant 270 using patterning and PVD, CVD, electrolytic plating,electroless plating process, or other suitable metal deposition process.Conductive layer 324 can be one or more layers of Al, Cu, Sn, Ni, Au,Ag, or other suitable electrically conductive material. Conductive layer324 is electrically connected to conductive layer 318 of interposer 316and operates, in part, as an RDL to extend the electrical connectivityof the interposer to external devices.

FIG. 21 shows FO-WLCSP 330 similar to the features described in FIGS. 13a-13 g and 14 with second interposer 332 stacked over interposer 244 byfit-press process to form multiple stepped interposers. The secondinterposer 332 has one or more conductive layers 334 and one or moreinsulating layers 336. Conductive layer 334 provides a verticalconduction path through interposer 332. Conductive layer 334 iselectrically connected to conductive layer 248 of interposer 244.

FIG. 22 shows FO-WLCSP 340 similar to the features described in FIGS. 13a-13 g and 14 with two-level stepped interposer 342 having one or moreconductive layers 344 and one or more conductive layers 346 and one ormore insulating layers 348. Conductive layers 344 and 346 provide avertical conduction path through interposer 342. Conductive layer 344 iselectrically connected between bumps 256 and conductive layer 278 ofbuild-up interconnect structure 274.

A semiconductor die or component 350 has an active surface 352containing analog or digital circuits implemented as active devices,passive devices, conductive layers, and dielectric layers formed withinthe die and electrically interconnected according to the electricaldesign and function of the die. For example, the circuit may include oneor more transistors, diodes, and other circuit elements formed withinactive surface 352 to implement analog circuits or digital circuits,such as DSP, ASIC, memory, or other signal processing circuit.Semiconductor die 350 may also contain IPD, such as inductors,capacitors, and resistors, for RF signal processing. Contact pads 354are electrically connected to the circuits on active surface 262.Semiconductor die 350 is mounted and electrically connected toconductive layer 346 of interposer 342 with bumps 356.

An encapsulant or molding compound 358 is deposited over interposer 342and around semiconductor die 252, 260, and 350 using a paste printing,compressive molding, transfer molding, liquid encapsulant molding,vacuum lamination, spin coating, or other suitable applicator.Encapsulant 358 can be polymer composite material, such as epoxy resinwith filler, epoxy acrylate with filler, or polymer with proper filler.Encapsulant 358 is non-conductive and environmentally protects thesemiconductor device from external elements and contaminants.

Semiconductor die 252 is electrically connected to semiconductor die 260through bumps 256, interposer 342, and conductive layer 278 of build-upinterconnect structure 274. Semiconductor die 350 is electricallyconnected to semiconductor die 252 and 260 through bumps 256 and 356,interposer 342, and conductive layer 278 of build-up interconnectstructure 274. FO-WLCSP 340 has stepped interposer 342 with an opencavity for containing semiconductor die 252 and 260 to reduce the heightof the package. Bumps 256 and 356 are relatively small, compared tobumps 280, which provides finer pitch and higher I/O count forsemiconductor die 252 and 260. The smaller bumps 256 and 356 alsoimprove control of bump collapse and reduce electrical shorting toadjacent conductive structures. The interposer 342 reduces theencapsulant flow pressure toward semiconductor die 252 and 260 to reducedie shifting during encapsulation.

While one or more embodiments of the present invention have beenillustrated in detail, the skilled artisan will appreciate thatmodifications and adaptations to those embodiments may be made withoutdeparting from the scope of the present invention as set forth in thefollowing claims.

What is claimed:
 1. A method of making a semiconductor device,comprising: providing a carrier; forming an interface layer over thecarrier; disposing a first substrate over the carrier; disposing asecond substrate over the carrier; disposing a first semiconductor dieover the first and second substrates electrically connected to the firstand second substrates; depositing an encapsulant over the firstsemiconductor die and over the first and second substrates; and removingthe carrier and interface layer.
 2. The method of claim 1, furtherincluding forming a plurality of bumps over the first and secondsubstrates.
 3. The method of claim 1, wherein disposing the first andsecond substrates includes simultaneously disposing the first and secondsubstrates over the carrier.
 4. The method of claim 1, further includingforming an electrical connection between the first and secondsubstrates.
 5. The method of claim 1, further including forming aninterconnect structure over a surface of the first substrate oppositethe first semiconductor die.
 6. The method of claim 1, further includingdisposing a second semiconductor die over the first substrate.
 7. Amethod of making a semiconductor device, comprising: providing a firstsubstrate; disposing a second substrate adjacent to the first substrate;disposing a first semiconductor die over the first substrateelectrically connected to the first substrate; and depositing anencapsulant over the first semiconductor die and over the first andsecond substrates.
 8. The method of claim 7, further including forming abump between the first semiconductor die and first substrate.
 9. Themethod of claim 7, further including disposing a passive component overthe first or second substrate.
 10. The method of claim 7, furtherincluding forming an interconnect structure over a surface of the firstsubstrate opposite the first semiconductor die.
 11. The method of claim7, further including forming an electrical connection between the firstand second substrates.
 12. The method of claim 7, further includingforming a bump over a surface of the first substrate opposite the firstsemiconductor die.
 13. The method of claim 7, further includingdisposing a second semiconductor die over the first semiconductor die.14. A semiconductor device, comprising: a first substrate; a secondsubstrate; a first semiconductor die disposed over the first and secondsubstrates; and an encapsulant deposited over the first semiconductordie and over the first and second substrates.
 15. The semiconductordevice of claim 14, further including a bump formed between the firstsemiconductor die and the second substrate.
 16. The semiconductor deviceof claim 14, wherein the first substrate includes a laminate interposer.17. The semiconductor device of claim 14, wherein the first substrateincludes a coefficient of thermal expansion (CTE) similar to a CTE ofthe semiconductor die.
 18. The semiconductor device of claim 14, whereinthe first semiconductor die includes a ball grid array.
 19. Thesemiconductor device of claim 14, further including a secondsemiconductor die disposed over the first substrate.
 20. A semiconductordevice, comprising: a first substrate; a second substrate; and a firstsemiconductor die disposed over the first and second substrates andelectrically connected to the first and second substrates.
 21. Thesemiconductor device of claim 20, further including a secondsemiconductor die disposed over the first substrate.
 22. Thesemiconductor device of claim 20, wherein the first substrate includes alaminate interposer.
 23. The semiconductor device of claim 20, whereinthe second substrate includes an insulating layer and a conductivelayer.
 24. The semiconductor device of claim 20, wherein the firstsubstrate includes a coefficient of thermal expansion (CTE) similar to aCTE of the semiconductor die.
 25. The semiconductor device of claim 20,further including a passive component disposed over the first substrate.